Digital Logic Design (EE2313)

Pre-requisite(s)

None

Recommended Book(s)

Digital Design, 4th Edition by Morris Mano and Michael D. Ciletti

Reference Book(s)

Digital Fundamentals by Thomas Floyd

Course Objectives

One of the main goals of this course is to teach students the fundamental concepts in classical digital design and to demonstrate clearly the way in which digital circuits are designed and analyzed today. The purpose is to make students familiar with modern hierarchy of digital hardware and enlighten them the state-of-the-art computer hardware design methodologies. Moreover, the contents of the course provide students the basic idea of how to design and simulate logic circuits.

Course Learning Outcomes (CLO)

CLO:1. Identify and explain fundamental concepts of digital logic design including basic and universal gates, number systems, binary coded systems, basic components of combinational and sequential circuits (Level: C2)

CLO:2. Demonstrate the acquired knowledge to apply techniques related to the design and analysis of digital electronic circuits including Boolean algebra and multi-variable Karnaugh map methods (Level: C3)

CLO:3. Analyze small-scale combinational and sequential digital circuits (Level: C4)

CLO:4. Design small-scale combinational and synchronous sequential digital circuit using Boolean algebra and K-maps (Level: C5)

Course Contents

Binary Systems
  • Introduction
  • Number Systems and Conversions
  • Arithmetic with number systems
  • Signed and unsigned number systems and their arithmetic
  • Binary Codes
Boolean Algebra & Logic Gates
  • Boolean Postulates & Theorems
  • Boolean Functions and their Complements
  • Sum of MinTerms & Product of MaxTerms
  • Standard forms & Canonical Forms
  • Digital logic gates
Gate level Minimization
  • Karnaugh maps
  • Multi-variable (2,3,4,5) K-maps
  • Don’t care conditions
  • Digital Circuits using Basic and Universal Gates
Combinational Logic
  • Analysis and Design
  • Code Converters
  • Adders & its types
  • Subtractors, Multiplier
  • Magnitude Comparator
  • Decoders and Encoders
  • Multiplexers
Sequential Circuits
  • Latches (SR Latch, D Latch)
  • Flip Flops ( D Flip Flop, JK Flip Flop, T Flip Flop)
  • Characteristic Tables, Characteristic Equations.
  • Design and Analysis of Clocked Sequential Circuits (State Equations, State Tables, State Diagrams)
  • Designing Counters
Registers & Counters
  • Simple registers
  • Registers with parallel Load
  • Shift Registers/Serial to parallel Convertors
  • Universal Shift Register
  • Asynchronous and Synchronous Counters
  • Ripple, Binary, BCD, & Johnson Counters
Introduction to Memories and Programmable Logic
  • RAM, ROM, PLA, PAL
  • SPLD, CPLD, FPGAs
Introduction to Verilog HDL

Mapping of CLOs to Program Learning Outcomes

CLOs/PLOs

CLO:1

CLO:2

CLO:3

 CLO:4

PLO:1 (Engineering Knowledge)

 

 

PLO:2 (Problem Analysis)

 

 

 

PLO:3 (Design and Development of Solutions)

 

 

 

PLO:4 (Investigation)

 

 

 

 

PLO:5 (Modern Tool Usage)

 

 

 

 

PLO:6 (The Engineer and Society)

 

 

 

 

PLO:7 (Environment and Sustainability)

 

 

 

 

PLO:8 (Ethics)

 

 

 

 

PLO:9 (Individual and Team Work)

 

 

 

 

PLO:10 (Communication)

 

 

 

 

PLO:11 (Project Management)

 

 

 

 

PLO:12 (Life Long Learning)