Title
Time Efficient Face Recognition for Real Time Applications
Abstract
Biometrics play an important role in enhancing efficiency and reliability of authentication systems. Face recognition is a non-intrusive type of biometric technique that can be used in security applications where individual controlled image acquisition is not possible such as crowd, airport, stadium etc. Significant efforts have been made by the researchers to improve accuracy and efficiency of face recognition system to meet the stringent needs of defense, security and high-tech commercial applications. For real-time face recognition system in a dynamic environment where the face database may change continuously and learning is a reemerging process, continuous calculation of Eigen values and vectors is a primary requirement.
For a face recognition system, fast PCA is modified by incorporating Modified Gram-Schmidt Orthogonalization (MGSO) for efficient Eigen values generation. An adaptive classifier is developed for modified fast PCA, which provides an optimum selection of leading Eigen vectors. Further, a technique is proposed using two dimensional data structure array to achieve the best combination of system variables for its improved accuracy.
In a pattern recognition solution, it is important to acquire meaningful data by evaluating Eigen values which is one of the most computational intensive parts of the system. For hardware evaluation of Eigen values, coordinate rotation digital computer (CORDIC) based on Jacobi algorithm (CJA) is one of the best reported FPGA implementations. Contrary to CJA, Householder (HH) is considered an efficient method for Eigen solution. A co-design pipelined architecture is developed to implement HH by using FPGA. The accuracy of HH is further improved by evaluating square root using non-restoring algorithm. The proposed architecture demonstrated an improvement up to 30% in time and 10-7 decimal places in accuracy compared to CJA.
MGSO applies normalization of vectors in its iterative orthogonal process. Normalization involves square root and other arithmetic operations. Hardware realization of the floating-point square root operation might be prohibitively expensive because of its complexity. Three architectures have been developed that employ fixed-point hardware for efficient implementation of normalization of vectors on an FPGA. The application dependent suitability of these architectures is evaluated by using four popular databases.
High accuracy, with minimum decision time is a challenging task for a real-time face recognition system. PCA is a classical approach amongst the dimension-reduced feature extraction methods towards efficient recognition. However, PCA offers poor accuracy because it treats faces as global entities. The Local Preserving Projection (LPP) and Orthogonal Local Preserving Projection (OLPP) methods treat faces as combination of features; however, they are computationally intensive.
A technique based on Frequency Distribution Curve (FDC) is developed which also preserves global as well as local features but it avoids matrix decomposition and other high order computational matrix operations. A software implementation of the technique showed an improvement up to 14%, 1.9% and 1.7% for the Yale, ORL and PIE databases respectively with relatively reduced training sets compared to PCA, LPP and OLPP.
FDC is formulated with a bias towards its hardware realization. An FPGA-based architecture has been developed by designing an adaptive pattern vector controller. This controller has the ability to detect high probability pattern vector for matching. The architecture performance is further improved by adopting parallelism which has demonstrated an improvement up to 80% compared to sequential operations. The system thus developed generally requires less than 200 ns to make a decision.